Possess 15 years of experience in Semiconductor Technology

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Expertise on Analog & Mixed Signal Layout, SERDES, GPIO & High speed IOs

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Done Full chip design for Power management: Floor plan, Placement, routing, verifications, LOGO, Seal ring, Scribe line, ID, Marker

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Technologies worked on – 3nm, 7nm, 10nm, 14nm, 16nm (FinFET), 20nm, 28nm, 45nm, 65nm, 90nm, 130nm, 180nm & 350nm

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Worked with various Fabs: Renesas, TSMC, Intel, TI, IBM, DongBu-HiTek, Micrel etc. 

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Worked SERDES14nm DKL: Rx_top, Bias_top, VGA, DFE, CDR, Refgen, Lane_top

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Analog blocks: BGR, LDO, PLL, Oscillator, Op-Amp, ADC, POR, Trim, Thermal-Sensors etc.

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High-speed IO blocks: bias-top, driver-bias, Level shifters, POR, detect-logic, R-Ladder, VREF_RX, LV & HV Schmitt etc.

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Developed and Verified the IO Libraries (Generic and CUP IOs) around 10 tap outs.

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Voltage domain worked: 1p0, 1p5, 1p8, 2p5, 2p8, 3p3, 5V & 28V

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Good on Memory and Standard cell layout design

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Handled the team up to 20 people.

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Guiding / Mentoring the team / Training / Technical Presentation / Involving in Proposal

Oct 2019 – Till date     FrenusTech Pvt. Ltd.                                        Technical Manager

Mar 2014 – Oct 2019  Wipro Limited (Bangalore)                              Architect (Technical)

Dec 2011 – Feb 2014  Infotech-Enterprises [Cyient] (Bangalore)                   Team Lead

June 2006 – Nov 2011            KPIT Cummins Infosystems (Bangalore)                     Team Lead

Sep 2004 - Jun 2006    CG-CoreEl (Bangalore)                                                Senior Design Engineer

B.E (Electrical and Electronics), Arunai Engineering College, Madras University, Chennai.

Certification

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Certificate course on VLSI Design at IETE Bangalore (CMOS Layout Design)

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Certificate course on CMOS Design Techniques at MS Ramaiah School of Advanced Studies

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Certificate Course on Foreign Language (Korean)

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 Attended Foreign Language (Japanese – JLPT4)

Current Project    IP Development (Op-amp & VCO)

Contribution          My responsibilities included:

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Schematic Analysis, Floor plan, placement, routing, verifications

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Taking care of matching, Critical signal routing, Half cell concepts

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Taking care of matching, Critical signal, EM, IR etc.

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It is a 7nm, TSMC process 

Environment         Virtuoso for Layout, Calibre for verifications 

Duration                3 Months

Project                   IP Development (GPIO, BGR, LDO, PLL)

Contribution          My responsibilities included:

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Schematic Analysis, Floor plan, placement, routing, verifications

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Floor plan, Power plan, ESD routing are challenges

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Taking care of matching, Critical signal, EM, IR etc.

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Verifications are LVS & DRC 

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It is a 45nm, TSMC process 

Environment         Virtuoso for Layout & Assura for Verifications

Duration                8 months

Project                   SERDES – 14nm: INTEL (USA) -Bangalore ODC 

Contribution          My responsibilities included:

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Handled and Delivered Rx_top block by interacting with sub-block (CBB) and top-block (Data lane) owners.

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Blocks: Rx_top, bias_top, VGA, DFE, CDR & REFGEN

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It is a 14nm DKL project from scratch layout

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Area & Effort estimation, Floor planning, Critical routing, shielding

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LV flow: Running around 40 different checks, Analyzed and fix them

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Challenges: Area & Time constraints, Different locations & vendors, 

Environment         Genoa Intel tool

Duration                10 months

Team size              20

Project                   MCD10 & TGL – Level shifters, monitor blocks: INTEL Bangalore ODC

Contribution          My responsibilities included:

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Worked on 10nm MIPI project from scratch layout

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Area estimation, Floor planning, Critical routing

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RV report analyzing and fixing: EM and IR, Fish & ploc stitching

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LV flow: Running around 40 different checks, Analyzed and fix them

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LVS, DRC, IPall, gnac, density, dfm, float, etc.

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10nm, INTEL (DPT) Dual Process Technology

Environment         GenA Intel tool

Duration                6 months

Team size              12

Project                   LDO, R-ladder blocks (@ Client place: INTEL Bangalore)

Contribution          My responsibilities included:

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MIFI project from scratch layout

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RV flow: Ploc generation, analyze the cgf file, over write files & no of modes

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RV report analyzing and fixing: EM and IR, Fish & ploc stitching

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LV flow: Running around 40 different checks. Analyze and fix them

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LVS, DRC, IPall, gnac, density, dfm, float, etc.

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14nm, INTEL (DPT) Dual Process Technology

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Worked with design sync environment (for version control)

Environment         Genoa Intel tool

Duration                1.5 year 

Team size              8 

Project                   High Speed IO Layout (@ Client place: XILINX and ODC)

Contribution          My responsibilities included:

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Worked on high speed IO Layout design

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Created leaf cells: D-flip flop, level shifters, logic control blocks, HV Schmitt, LV Schmitt, VREF signal generator, POR, Decaps (MOM & MIM), R-Ladders, rx & tx.

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16nm, TSMC (DPT) Dual Process Technology

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Worked with design sync environment (for version control)

Environment         Cadence Virtuoso XL Layout Editor, Calibre for verifications

Duration                12 months

Team size              11 

Project                   Analog and RF Layout (@ Client place: QUALCOMM)

Contribution          My responsibilities included:

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Worked on Analog and RF layout design

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Created leaf cells and done the DRC & LVS verifications

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28nm TSMC Process Technology

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Worked with design sync environment (for version control)

Environment         Cadence Virtuoso XL Layout Editor

Duration                2 months

Team size              5 

Project                   High Speed IO Layout (@ Client place: XILINX)

Contribution          My responsibilities included:

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Worked on high speed IO Layout design

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Created leaf cells and done DRC & LVS verifications (with G-rules)

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It’s a pitched layout for Metals and polys

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20nm, TSMC (DPT) Dual Process Technology

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Worked with design sync environment (for version control)

Environment         Cadence Virtuoso XL Layout Editor, Calibre for verifications

Duration                2 months

Team size              4 

Project                   Supervisor IC – Micrel USA: Bangalore ODC

Contribution          My responsibilities included:

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Involved in full chip creation 

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Die area calculation & effort estimation

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Leaf cell creation, floor planning (BGR, IBIAS, Sense comp, Trim circuit, Driver)

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Top level integration and ESD place & route

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Chip finishing (Logo ID, Graffiti) & Tap out 

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Dongbu (South Korea) 0.18um, 2P3M, 5V process, 6pin Thin MLF package              

Environment         Cadence Virtuoso-XL Layout Editor, Assura for verifications

Duration                 3 Months

Team size              4 

Project                   MIC2782 – Micrel USA: Bangalore ODC

Contribution          My responsibilities included:

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Involved full chip creation & Leading the team

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Die area Estimation and Pad placement

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Floor planning, power rail planning, Seal ring & Scribe line

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Critical block place and route (Oscillator – Core, bias & Trim, POR)

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ESD placement and routing

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Shield the critical signal & Power line separation for critical and digital blocks

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Top level integration

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