Talent Information
Resume Photo
Full Name
Thulasi**
(Mal,
49세, 1975년생)
주소
28/1 Venkatapura, Koramangala Bangalore - India
TEL
no input
HP
919-8862-9323
E-Mail
a_thulsi@yahoo.com
Force status
Exemption
Final education
Graduation from a college
Desired job conditions
Desired working area
AMS Layout design > custom layout design
A desired occupation
Production/Construction > Etc
Hope to find a job
Hope salary
Remarks
QA Ability
- Word (Hangul · MS Word)(Advanced)
- Presentation (PowerPoint)(Advanced)
- Spreadsheet (Excel)(Advanced)
- Internet (Information Retrieval)(Advanced)
Foreign language ability
English(Advanced)
Certification Hold
- Korean basic language (.)
Career items
Career items
- 14-03-2021 Dear Sir/Madam, I have 15 years of experience in VLSI domain. Prefer to work hands-on and groom the Layout team (AMS, SERDES, IO, Memory layout domains). Have rich experience an Analog & Mixed Signal Layout, SERDES (Rx_top block that has bias_top, VGA, DFE, CDR & Refgen) and Done more than 10 IO library tape outs. Have done full chip layout design, integration, Verification & Tape out for PMIC. Worked on Various Fabs like TSMC, TI, Dongbu (Korea), MICREL & RENESAS. Technology worked on from 3nm, 7nm, 10nm, 14nm, 16nm (FINFET), 28nm, 45nm, 60nm, 90nm to 350nm. An Analog IPs worked on LDO, BGR, PLL, POR, CAP banks & RES banks. Handled up to 20 members team technically. Guiding, Mentoring, Training, Technical Presentation, Involving in Proposals & Client meetings. Involving in Lateral hiring & Campus requirement. Pls. find the attached CV herewith. Thanks and regards -Thulsi (M-9886293237)
Self introduction
SummAry
Possess 15 years of experience in Semiconductor Technologyv Expertise on Analog & Mixed Signal Layout, SERDES, GPIO & High speed IOs
v Done Full chip design for Power management: Floor plan, Placement, routing, verifications, LOGO, Seal ring, Scribe line, ID, Marker
v Technologies worked on – 3nm, 7nm, 10nm, 14nm, 16nm (FinFET), 20nm, 28nm, 45nm, 65nm, 90nm, 130nm, 180nm & 350nm
v Worked with various Fabs: Renesas, TSMC, Intel, TI, IBM, DongBu-HiTek, Micrel etc.
v Worked SERDES14nm DKL: Rx_top, Bias_top, VGA, DFE, CDR, Refgen, Lane_top
v Analog blocks: BGR, LDO, PLL, Oscillator, Op-Amp, ADC, POR, Trim, Thermal-Sensors etc.
v High-speed IO blocks: bias-top, driver-bias, Level shifters, POR, detect-logic, R-Ladder, VREF_RX, LV & HV Schmitt etc.
v Developed and Verified the IO Libraries (Generic and CUP IOs) around 10 tap outs.
v Voltage domain worked: 1p0, 1p5, 1p8, 2p5, 2p8, 3p3, 5V & 28V
v Good on Memory and Standard cell layout design
v Handled the team up to 20 people.
v Guiding / Mentoring the team / Training / Technical Presentation / Involving in Proposal
PROFESSIONAL EXPERIENCE
Oct
2019 – Till date FrenusTech Pvt. Ltd. Technical
Manager
Mar
2014 – Oct 2019 Wipro Limited (Bangalore) Architect
(Technical)
Dec
2011 – Feb 2014 Infotech-Enterprises [Cyient]
(Bangalore) Team Lead
June
2006 – Nov 2011 KPIT Cummins
Infosystems (Bangalore) Team Lead
Sep 2004 - Jun 2006 CG-CoreEl (Bangalore) Senior
Design Engineer
Education
B.E (Electrical and Electronics), Arunai
Engineering College, Madras University, Chennai.
Certification· Certificate course on VLSI Design at IETE Bangalore (CMOS Layout Design)
· Certificate course on CMOS Design Techniques at MS Ramaiah School of Advanced Studies
· Certificate Course on Foreign Language (Korean)
· Attended Foreign Language (Japanese – JLPT4)
SKILLS
PROJECTS
Current Project IP Development (Op-amp & VCO)
Contribution My responsibilities included:
· Schematic Analysis, Floor plan, placement, routing, verifications
· Taking care of matching, Critical signal routing, Half cell concepts
· Taking care of matching, Critical signal, EM, IR etc.
· It is a 7nm, TSMC process
Environment Virtuoso for Layout, Calibre for verifications
Duration 3 Months
Project IP Development (GPIO, BGR, LDO, PLL)
Contribution My responsibilities included:
· Schematic Analysis, Floor plan, placement, routing, verifications
· Floor plan, Power plan, ESD routing are challenges
· Taking care of matching, Critical signal, EM, IR etc.
· Verifications are LVS & DRC
· It is a 45nm, TSMC process
Environment Virtuoso for Layout & Assura for Verifications
Duration 8 months
Project SERDES – 14nm: INTEL (USA) -Bangalore ODC
Contribution My responsibilities included:
· Handled and Delivered Rx_top block by interacting with sub-block (CBB) and top-block (Data lane) owners.
· Blocks: Rx_top, bias_top, VGA, DFE, CDR & REFGEN
· It is a 14nm DKL project from scratch layout
· Area & Effort estimation, Floor planning, Critical routing, shielding
· LV flow: Running around 40 different checks, Analyzed and fix them
· Challenges: Area & Time constraints, Different locations & vendors,
Environment Genoa Intel tool
Duration 10 months
Team size 20
Project MCD10 & TGL – Level shifters, monitor blocks: INTEL Bangalore ODC
Contribution My responsibilities included:
· Worked on 10nm MIPI project from scratch layout
· Area estimation, Floor planning, Critical routing
· RV report analyzing and fixing: EM and IR, Fish & ploc stitching
· LV flow: Running around 40 different checks, Analyzed and fix them
· LVS, DRC, IPall, gnac, density, dfm, float, etc.
· 10nm, INTEL (DPT) Dual Process Technology
Environment GenA Intel tool
Duration 6 months
Team size 12
Project LDO, R-ladder blocks (@ Client place: INTEL Bangalore)
Contribution My responsibilities included:
· MIFI project from scratch layout
· RV flow: Ploc generation, analyze the cgf file, over write files & no of modes
· RV report analyzing and fixing: EM and IR, Fish & ploc stitching
· LV flow: Running around 40 different checks. Analyze and fix them
· LVS, DRC, IPall, gnac, density, dfm, float, etc.
· 14nm, INTEL (DPT) Dual Process Technology
· Worked with design sync environment (for version control)
Environment Genoa Intel tool
Duration 1.5 year
Team size 8
Project High Speed IO Layout (@ Client place: XILINX and ODC)
Contribution My responsibilities included:
· Worked on high speed IO Layout design
· Created leaf cells: D-flip flop, level shifters, logic control blocks, HV Schmitt, LV Schmitt, VREF signal generator, POR, Decaps (MOM & MIM), R-Ladders, rx & tx.
· 16nm, TSMC (DPT) Dual Process Technology
· Worked with design sync environment (for version control)
Environment Cadence Virtuoso XL Layout Editor, Calibre for verifications
Duration 12 months
Team size 11
Project Analog and RF Layout (@ Client place: QUALCOMM)
Contribution My responsibilities included:
· Worked on Analog and RF layout design
· Created leaf cells and done the DRC & LVS verifications
· 28nm TSMC Process Technology
· Worked with design sync environment (for version control)
Environment Cadence Virtuoso XL Layout Editor
Duration 2 months
Team size 5
Project High Speed IO Layout (@ Client place: XILINX)
Contribution My responsibilities included:
· Worked on high speed IO Layout design
· Created leaf cells and done DRC & LVS verifications (with G-rules)
· It’s a pitched layout for Metals and polys
· 20nm, TSMC (DPT) Dual Process Technology
· Worked with design sync environment (for version control)
Environment Cadence Virtuoso XL Layout Editor, Calibre for verifications
Duration 2 months
Team size 4
Project Supervisor IC – Micrel USA: Bangalore ODCContribution My responsibilities included:
· Involved in full chip creation
· Die area calculation & effort estimation
· Leaf cell creation, floor planning (BGR, IBIAS, Sense comp, Trim circuit, Driver)
· Top level integration and ESD place & route
· Chip finishing (Logo ID, Graffiti) & Tap out
· Dongbu (South Korea) 0.18um, 2P3M, 5V process, 6pin Thin MLF package
Environment Cadence Virtuoso-XL Layout Editor, Assura for verifications
Duration 3 Months
Team size 4
Project MIC2782 – Micrel USA: Bangalore ODCContribution My responsibilities included:
· Involved full chip creation & Leading the team
· Die area Estimation and Pad placement
· Floor planning, power rail planning, Seal ring & Scribe line
· Critical block place and route (Oscillator – Core, bias & Trim, POR)
· ESD placement and routing
· Shield the critical signal & Power line separation for critical and digital blocks
· Top level integration
·